1. Field of the Invention
The present invention relates to virtual storage address space access control for referring to data on an arbitrary virtual address space in an information processor having a virtual storage unit which provides a plurality of virtual address spaces in a physical address space, and specifically relates to determination of a segment table to be used for translating a virtual address designated by an application program into a physical address, based on an access register (AR) designated by the application program, in virtual storage address space access control.
A recent demand on an information processing system is to increase the amount of data to be processed. This is particularly remarkable in a database system. Due to this demand, there is required an architecture which enables a user program to directly access data in a plurality of address spaces, beyond a limitation of an address space in a conventional virtual storage unit. In such a case, it is desired-to improve performance and to simplify circuitry, because of the complexity of the process for translating a virtual address designated by a user program into a physical address.
2. Description of the Related Art
Systems capable of referring to a plurality of virtual address spaces from a user program as mentioned above, include a system utilizing an access register (hereinafter abbreviated to xe2x80x9cARxe2x80x9d). In a system which extends an accessible address space utilizing such an AR, one of a plurality of AR""s (e.g., sixteen AR""s from AR0 to AR15) is designated by an instruction by which a user program accesses a memory. There is then taken out an access list entry token (hereinafter called xe2x80x9cALETxe2x80x9d) from the designated AR, and there is decided a segment table designation (hereinafter abbreviated to xe2x80x9cSTDxe2x80x9d) based on the ALET, via processing of access register translation (hereinafter abbreviated to xe2x80x9cARTxe2x80x9d). The STD designates one of segment tables and, similarly to the conventional method, a logical address in a virtual space is translated into an actual address, making use of the segment table via processing of dynamic address translation (hereinafter abbreviated to xe2x80x9cDATxe2x80x9d). An application program is allowed to access to a plurality of address spaces, making use of a plurality of AR""s.
Since the above processing of ART requires a long period of time for processing, there can be adopted a two stage-type of ART index buffering mechanism to thereby shorten an effective processing time (e.g., refer to Japanese Unexamined Patent Publication (Kokai) No. 3-57046). The second stage of the buffering mechanism is called an ART look-up buffer (ALB). In the present specification, the first stage buffering mechanism is called an STD array.
In the above described prior art, entries in an STD array (this array is called xe2x80x9cfirst ALBxe2x80x9d in the aforementioned Publication) include STD""s corresponding to AR""s, respectively, and each of these entries is accessed by an AR number (ARN). When an STD corresponding to the designated AR is validly stored in the STD array, the intended STD can be taken out immediately. When an STD corresponding to the designated AR is not validly stored in the STD array, then the ALB is looked up. Each entry in the ALB includes an ALET and an STD paired with and translated from the ALET, so that an STD can be obtained by retrieving an entry which corresponds to an ALET of the designated AR. The thus obtained STD is entered into the STD array. Only when the designated AR does not hit the ALB, is there performed a calculation for translating the ALET into the STD and the thus obtained STD is entered into both of the ALB and STD array.
In the above prior art, the fact-that each entry in the. STD array is accessed by an ARN means that fixed one-to-one correspondences are previously set between the AR""s and the entries in the STD array, respectively. Therefore, there are required as many STD storing areas as there are AR""s. For example, sixteen STD storing areas are required when sixteen AR""s are used.
Meanwhile, it is probable that an actually adopted user application accesses the same space using some different AR""s, i.e., a plurality of AR""s correspond to the same STD. This means that entries in an STD array are used in an excessive number more than really required. Should an STD array be prepared in an excessive size for such an application, there is caused such a problem that a circuit scale is increased as compared to a situation where the array is prepared in a required minimum size, and that a circuit delay is thus increased.
In case of providing STD storing areas only in a required number (e.g., four) in an STD array, there is required some mechanism for indicating a relationship between the AR""s and the entries of STD array. As a technique therefor, it might be envisaged that ALET""s corresponding to respective STD entries are stored in a manner related to the STD""s, to thereby obtain an STD related to an ALET coinciding with an ALET of a designated AR. However, it is then required to compare the ALET of the designated AR with the stored ALET""s at each access, and this becomes a bottleneck in shortening a machine cycle.
It is therefore an object of the present invention to provide a method for swiftly determining an STD which corresponds to a designated AR, making use of a small sized circuit.
According to the present invention, there is provided a virtual storage address space access control method of determining a segment table to be used for accessing to the virtual address space, based on a designated AR (access register), the method comprising the steps of: dynamically storing correspondences between AR""s and STD""s (segment table designations) stored in an STD array, into an AR map; and determining an STD which corresponds to a designated AR, making use of the correspondences stored in the AR map.
It is preferable that said method further comprises the step of: storing copies of ALET""s (access list entry tokens) which correspond to respective STD""s stored in the STD array; wherein said dynamically storing step includes the substep of: comparing an ALET of the designated AR with each of the copies of ALET""s; storing an STD determined from the ALET of the designated AR, in the STD array, when the ALET of the designated AR coincides with none of the copies of ALET""s; and storing a correspondence between the designated AR and an STD corresponding to a copy of an ALET which coincides with the ALET of the designated AR, into the AR map.
According to the present invention, there is also provided a virtual storage address space access control apparatus for determining a segment table to be used for accessing the virtual address space, based on a designated AR, comprising: an AR map capable of dynamically storing correspondences between AR""s and STD""s stored in an STD array; and an access control circuit determining an STD which corresponds to a designated AR, making use of the correspondences stored in the AR map.
It is preferable that said apparatus further comprises: a memory storing copies of ALET""S which correspond to respective STD""s stored in the STD array; wherein said access control circuit includes: a comparator comparing an ALET of the designated AR with each of the copies of ALET""s; an STD array control circuit storing-an STD determined from the ALET of the designated AR, in the STD array, when the ALET of the designated AR coincides with none of the copies of ALET""s; and AR map control circuit storing a correspondence between the designated AR and an STD corresponding to a copy of an ALET which coincides with the ALET of the designated AR, into the AR map.